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DS1238 micromanager DS1238 022698 1/13 features ? holds microprocessor in check during power transients ? halts and restarts an out-of-control microprocessor ? warns microprocessor of an impending power failure ? converts cmos sram into nonvolatile memory ? unconditionally write protects memory when power supply is out of tolerance ? delays write protection until completion of the current memory cycle ? consumes less than 200 na of battery current ? controls external power switch for high current applications ? debounces pushbutton reset ? accurate 10% power supply monitoring ? optional 5% power supply monitoring designated DS1238-5 ? provides orderly shutdown ini mcroprocessor appli- cations ? pin-for-pin compatible with max691 ? standard 16-pin dip or space-saving 16-pin soic ? optional industrial temperature range -40 c to +85 c pin assignment vbat vcco vcc gnd pf oscin oscsel rst in rst rvt wds cei ceo st nmi 16-pin dip (300 mil.) see mech. drawings section 1 11 12 13 14 2 3 4 5 6 7 8 9 10 15 16 vbat vcco vcc gnd pf rst rst cei ceo st nmi in 16-pin soic (300 mil.) see mech. drawings section rvt oscin oscsel wds 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pin description v bat +3 volt battery input v cco switched sram supply output v cc +5 volt power supply input gnd ground pf power fail rvt reset voltage threshold oscin oscillator in oscsel oscillator select in early warning input nmi nonmaskable interrupt st strobe input ceo chip enable output cei chip enable input wds watchdog status rst reset output (active low) rst reset output (active high) description the DS1238 micromanager provides all the necessary functions for power supply monitoring, reset control, and memory backup in microprocessor-based systems. a precise internal voltage reference and comparator cir- cuit monitor power supply status. when an out-of-toler- ance condition occurs, the microprocessor reset and power fail outputs are forced active, and static ram control unconditionally write protects external memory. the DS1238 also provides early warning detection of a user-defined threshold by driving a non-maskable inter- rupt. external reset control is provided by a pushbutton reset debounce circuit connected to the rst pin. an in- ternal watchdog timer can also force the reset outputs to the active state if the strobe input is not driven low prior to watchdog timeout. oscillator control pins oscsel and oscin provide either external or internal clock tim- ing for both the reset pulse width and the watchdog time- out period. the watchdog status and reset voltage threshold are provided via wds and rvt , respectively. a block diagram of the DS1238 is shown in figure 1.
DS1238 022698 2/13 pin description pin name description v bat +3v battery input provides nonvolatile operation of control functions. v cco v cc output for nonvolatile sram applications. v cc +5v primary power input. gnd system ground. pf power fail indicator, active high, used for external power switching as shown in figure 9. rvt reset voltage threshold. indicates that v cc is below the reset voltage threshold. oscin oscillator input or timing capacitor. see table 1. oscsel oscillator select. selects internal or external clock functions. see table 1. in early warning power fail input. this voltage sense point may be tied (via resistor divider) to a user-selected voltage. nmi non-maskable interrupt. output used in conjunction with the in pin to indicate an impending power failure. st strobe input. a hightolow transition will reset the watchdog timer, indicating that software is still in control. ceo chip enable output. write protected. used with nonvolatile sram applications. cei chip enable input. wds watchdog status. indicates that a watchdog timeout has occurred. rst active low reset output. rst active high reset output. power monitor the DS1238 employs a band gap voltage reference and a precision comparator to monitor the 5volt supply (v cc ) in microprocessor-based systems. when an out-of-tolerance condition occurs, the rvt , rst, and rst outputs are driven to the active state. the v cc trip point (v cctp ) is set for 10% operation so that the rvt , rst and rst outputs will become active as v cc falls below 4.5 volts (4.37 typical). the v cctp for the 5% op- eration option (DS1238-5) is set for 4.75 volts (4.62 typi- cal). the rst and rst signals are excellent for micro- processor reset control, as processing is stopped at the last possible moment of in-tolerance v cc . on power up, rvt will become inactive as soon as v cc rises above v cctp . however, the rst and rst signals remain ac- tive for a minimum of 50 ms (100 ms typical) after v cctp is reached to allow the power supply and microproces- sor to stabilize.
DS1238 022698 3/13 DS1238 functional block diagram figure 1 digital bandgap in rst pf 30khz ring 1.27v 2.54v reset pulse watchdog watchdog strobe status latch oscillator externally oscin oscsel v cc v bat v cco rvt wds st cei rst ceo ce control nmi sampler rst push button monitor oscillator reference digital sampler generator status latch timer select controlled oscillator
DS1238 022698 4/13 watchdog timer the DS1238 provides a watchdog timer function which forces the wds , rst, and rst signals to the active state when the strobe input (st ) is not stimulated for a predetermined time period. this time period is de- scribed below in table 1. the watchdog timeout period begins as soon as rst and rst are inactive. if a high-to-low transition occurs at the st input prior to time out, the watchdog timer is reset and begins to time out again. the st input timing is shown in figure 2. in order to guarantee that the watchdog timer does not timeout, a high-to-low transition on st must occur at or less than the minimum timeout of the watchdog as described in the ac electrical characteristics. if the watchdog timer is allowed to time out, the wds , rst, and rst outputs are driven to the active state. wds is a latched signal which indicates the watchdog status, and is activated as soon as the watchdog timer completes a full period as outlined in table 1. the wds pin will remain low until one of three operations occurs. the first is to strobe the st pin with a falling edge, which will both set the wds as well as the watchdog timer count. the second is to leave the st pin open, which disables the watchdog. lastly, the wds pin is active low whenever v cc falls below v cctp and activates the rvt signal. the st input can be derived from microprocessor address, data, or con- trol signals, as well as microcontroller port pins. under normal operating conditions, these signals would rou- tinely reset the watchdog timer prior to time out. the watchdog is disabled by leaving the st input open, or as soon as v cc falls to v cctp . nonmaskable interrupt the DS1238 generates a non-maskable interrupt (nmi ) for early warning of a power failure to the microproces- sor. a precision comparator monitors the voltage level at the in pin relative to an on-chip reference generated by an internal band gap. the in pin is a high impedance in- put allowing for a user-defined sense point. an external resistor voltage divider network (figure 5) is used to in- terface with high voltage signals. this sense point may be derived from the regulated 5-volt supply, or from a higher dc voltage level closer to the main system power input. since the in trip point v tp is 1.27 volts, the proper values for r1 and r2 can be determined by the equation as shown in figure 5. proper operation of the DS1238 requires that the voltage at the in pin be limited to v ih . therefore, the maximum allowable voltage at the supply being monitored (v max ) can also be derived as shown in figure 5. a simple approach to solving this equation is to select a value for r2 of high enough value to keep power consumption low, and solve for r1. the flexibility of the in input pin allows for detection of power loss at the earliest point in a power supply system, maximizing the amount of time for microprocessor shut-down be- tween nmi and rst or rst . when the supply being monitored decays to the voltage sense point, the DS1238 will force the nmi output to an active state. noise is removed from the nmi power fail detection circuitry using built-in time domain hysteresis. that is, the monitored supply is sampled periodically at a rate determined by an internal ring oscillator running at approximately 30 khz (33 m s/cycle). three consecutive samplings of out-of-tolerance supply (below v sense ) must occur at the in pin to active nmi . therefore, the supply must be below the voltage sense point for ap- proximately 100 m s or the comparator will reset. in this way, power supply noise is removed from the monitoring function preventing false trips. during a powerup, any in pin levels below v tp detected by the comparator are disabled from reaching the nmi pin until v cc rises to v cctp . as a result, any potential active nmi will not be initiated until v cc reaches v cctp . removal of an active low level on the nmi pin is con- trolled by the subsequent rise of the in pin above v tp . the initiation and removal of the nmi signal during pow- er up depends on the relative voltage relationship be- tween v cc and the in pin voltage. note that a fast slew- ing power supply may cause the nmi to be virtually non-existent on power up. this is of no consequence however, since an rst will be active. the nmi voltage will follow v cc down until v cc decays to v bat . once v cc decays to vbat , the nmi pin will enter a tri-state mode. st input timing figure 2 t st t td v ih st
DS1238 022698 5/13 oscillator controls table 1 watchdog timeout period (typ) oscin oscsel first period following a reset other timeout reset active duration external ext clk low 20480 clks 5120 clocks 641 clks ext cap low 2.2 sec 47 pf xcpf 550 ms 47 pf xcpf 69 ms 47 pf xcpf internal low hi/open 2.7 sec 170 ms 85 ms hi/open hi/open 2.7 sec 2.7 sec 85 ms note that the oscin and oscsel pins are tri-stated when v cc is below v bat . power monitor, watchdog timer, and pushbutton reset figure 3 gnd rst rst port 1 DS1238 8051 m p 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 +3 v dc v cc +5 v dc st rst v bat pushbutton reset timing figure 4 pushbutton closure on rst pushbutton release of rst t pb t rst v oh v il rst rst v ol v oh v ol
DS1238 022698 6/13 non-maskable interrupt figure 5 gnd rst voltage sense point r1 r2 to microprocessor in DS1238 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nmi rst v cc +5 v dc +3 v dc v bat v sense r1 r2 r2 x1.27 maxvoltage v sense 1.27 x5.0 vmax example 1: 5 volt supply, r2 = 10k ohms, v sense = 4.8 volts 4.8 r1 10k 10k x1.27 r1 27.8k ohm example 2: 12 volt supply, r2 = 10k ohms, v sense = 9.0 volts 9.0 r1 10k 10k x1.27 r1 60.9k ohm v max 9.00 1.27 x5.0 35.4 volts nmi from in input figure 6 nmi in t ipd v ol v tp
DS1238 022698 7/13 memory backup the DS1238 provides all of the necessary functions re- quired to battery back a static ram. first, an internal switch is provided to supply sram power from the pri- mary 5-volt supply (v cc ) or from an external battery (v bat ), whichever is greater. second, the same power fail detection described in the power monitor section is used to hold the chip enable output (ceo ) to within 0.3 volts of v cc or to within 0.7 volts of v bat . the output volt- age diode drop from v bat (0.7 v) is necessary to pre- vent charging of the battery in violation of ul standards. write protection occurs as v cc falls below v cctp as specified. if cei is low at the time power fail detection occurs, ceo is held in its present state until cei is re- turned high, or the period t ce expires. this delay of write protection until the current memory cycle is completed prevents the corruption of data. if ceo is in an inactive state at the time of v cc fail detection, ceo will be un- conditionally disabled within t cf . during nominal supply conditions ceo will follow cei with a maximum propa- gation delay of 20 ns. figure 7 shows a typical nonvola- tile sram application. freshness seal in order to conserve battery capacity during storage and/or shipment of an end system, the DS1238 pro- vides an internal freshness seal to electrically discon- nect the battery. figure 8 depicts the three pulses below ground on the in pin required to invoke the freshness seal. the freshness seal will result in the tri-state of out- puts v cco , rst, rst , and ceo . the wds output will be driven active low. the pf pin is not disabled by the freshness mode and will continue to source power from the v bat pin whenever v cc is below v bat . the fresh- ness seal will be disconnected and normal operation will begin when v cc is cycled and reapplied to a level above v bat . to prevent negative pulses associated with noise from setting the freshness mode in system applications, a se- ries diode and resistor can be used to shunt noise to ground. during manufacturing, the freshness seal can still be set by holding tp2 at -3 volts while applying the 0 to -3-volt clock to tp1. power switching when larger operating currents are required in a bat- tery-backed system, the internal switching devices of the DS1238 may be too small to support the required load through v cco with a reasonable voltage drop. for these applications, the pf output is provided to gate ex- ternal power switching devices. as shown in figure 9, power to the load is switched from v cc to battery on power down, and from battery to v cc on power up. the ds1336 is designed to use the pf output to switch be- tween v bat and v cc . it provides better leakage and switchover performance than currently available dis- crete components. the transition threshold for pf is set to the external battery voltage v bat , allowing a smooth transition between sources. any load applied to the pf pin by an external switch will be supplied by the battery. therefore, if a discrete switch is used, this load should be taken into consideration when sizing the battery. nonvolatile sram figure 7 gnd rst sram to u p +3v from decoder DS1238 +5 v dc v bat v cco v cc cei ceo rst ce v cc
DS1238 022698 8/13 freshness seal figure 8 note: this series of pulses must be applied during normal +5 volt operation. from voltage sense point 100 ohms 0 volts 1 ms in -3 volts in tp1 tp2 power switching figure 9 pf gnd rst gnd pf to u p from decoder to sram +3v battery DS1238 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ds1336 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 +5 v dc in2 in4 v bat02 out4 v batin v cco v cc rst cei ceo pf out5 in5 v bat to sram v cc v cc /in1 out1 out2 out3 v bat01 in3 note: if freshness on the DS1238 is not used, pf on the ds1336 may be tied to out1. this will free in4, out4, and v bat01 for system use. timing diagrams this section provides a description of the timing dia- grams shown in figure 10 and figure 11. figure 10 il- lustrates the relationship for power down. as v cc falls, the in pin voltage drops below v tp . as a result, the pro- cessor is notified of an impending power failure via an active nmi . this gives the processor time to save critical data in nonvolatile sram. as the power falls further, v cc crosses v cctp , the power monitor trip point. when v cc reaches v cctp , and active rst and rst are given. at this time, ceo is brought high to write protect the ram. when the v cc reaches v bat , a power fail is is- sued via the pf pin. figure 11 shows the power up sequence. as v cc slews above v bat , the pf pin is deactivated. an active reset occurs as well as an nmi . although the nmi may be short due to slew rates, reset will be maintained for the standard t rpu timeout period . at a later time, if the in pin falls below v tp , a new nmi will occur. if the processor does not issue an st , a watchdog reset will also occur. the second nmi and rst are provided to illustrate these possibilities.
DS1238 022698 9/13 power down timing figure 10 4.5 4.25 tf rst pf v cc t ipd v oh v ih v il v ol t ppf t cf pf = v ohl t pd in pin = v tp v cc = v cctp v cc = v bat v cc = 0 v t rpd nmi rst ceo cei cei ceo = 0 v ceo = v ohl rst = 0v rst slews with v cc nmi = 0 v nmi = tri-state nmi slews with v cc v ol v oh
DS1238 022698 10/13 power up timing figure 11 t ppf 4.5 4.25 rst t ipd v ol v ih v ol pf = v ohl in pin = v tp v cc = v cctp v cc = v bat v cc = 0 v cei ceo = 0 v ceo = v ohl nmi = tri-state t ipd t rst v ol v ol v oh t pd t rec v il rst t rpu t r v ol
DS1238 022698 11/13 absolute maximum ratings* voltage on v cc pin relative to ground 0.5v to +7.0v voltage on i/o relative to ground 0.5v to v cc + 0.5v voltage on in pin relative to ground 3.5v to v cc + 0.5v operating temperature 0 c to 70 c operating temperature (industrial version) 40 c to +85 c storage temperature -55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes supply voltage v cc 4.5 5.0 5.5 v 1 supply voltage (5% option) v cc 4.75 5.0 5.5 v 1 input high level v ih 2.0 v cc +0.3 v 1 input low level v il -0.3 +0.8 v 1 in input pin v in 0 v cc v 1 battery input v bat 2.7 4.0 v 1 dc electrical characteristics (0 c to 70 c; v dd = 5v + 10%) parameter symbol min typ max units notes supply current i cc 4 ma 2 battery current i bat 0 200 na 2 , 12 supply output current (v cco = v cc - 0.3v) i cc01 100 ma 3 supply out current (v cc < v bat ) i cc02 1 ma 4 supply output voltage v cco v cc -0.3 v 1 battery back voltage v cco v bat -0.8 v 6 low level @ rst v ol 0.4 v 1 output voltage @ 500 m a v oh v cc 0.5v v cc 0.1v v 1 ceo and pf output v ohl v bat -0.8 v 6 input leakage current i li -1.0 +1.0 m a 121 output leakage i lo -1.0 +1.0 m a output current @0.4v i ol 4.0 ma 9 output current @2.4v i oh -1.0 ma 10 power sup. trip point v cctp 4.25 4.37 4.50 v 1 power supply trip (5% option) v cctp 4.50 4.62 4.75 v in input pin current i ccin -1.0 +1.0 m a in input trip point v tp 1.15 1.27 1.35 v 1
DS1238 022698 12/13 ac electrical characteristic (0 c to 70 c; v cc = 5v+ 10%) parameter symbol min typ max units notes v cc fall detect to rst, rst t rpd 40 100 175 m s v tp to nmi t ipd 40 100 175 m s reset active oscsel=high t rst 40 85 150 ms st pulse width t st 20 ns 13 pbrst @ v il t pb 30 ms v cc slew rate 4.75 to 4.25 t f 300 m s chip enable prop delay t pd 20 ns v cc fail to chip enable high t cf 7 12 144 m s 11 v cc valid to rst (rc = 1) t fpu 100 ns v cc valid to rst t rpu 40 100 150 ms 5 v cc slew to 4.25 to v bat t fb1 10 m s chip enable output recovery time t rec 0.1 m s 7 v cc slew 4.25 to 4.75 t r 0 m s chip enable pulse width t ce 5 m s 8 watchdog time delay int clock long period t td 1.7 2.7 s short period 110 170 ms watchdog time delay, ext clock, after reset t td 20480 clocks normal 5120 clocks v bat detect to pf t ppf 2 m s osc in frequency f osc 0 250 khz capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 5 pf output capacitance c out 7 pf
DS1238 022698 13/13 notes: 1. all voltages referenced to ground. 2. measured with v cco , ceo , pf, st , rst, rst , and nmi pin open. 3. i cco1 is the maximum average load which the DS1238 can supply at v cc -.3v through the v cco pin during normal 5-volt operation. 4. i cco2 is the maximum average load which the DS1238 can supply through the v cco pin during data retention battery supply operation, with a maximum drop of 0.8 volts for commercial, 1.0v for industrial. 5. with t r = 5 m s. 6. v cco is approximately v bat -0.5v at 1 m a load. 7. t rec is the minimum time required before cei /ceo memory access is allowed. 8. t ce maximum must be met to insure data integrity on power loss. 9. all outputs except rst which is 25 m a max. 10. all outputs except rst , rvt , and nmi which is 25 m a min. 11. the st pin will sink + 50 m a in normal operation. the oscin pin will sink + 5 m a in normal operation. the oscsel pin will sink + 10 m a in normal operation. 12. i bat is measured with v bat =3.0v. 13. st should be active low before the watchdog is disabled (i.e., before the st input is tristated). tri +5v st output 3.3 k w 2.2 k w

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